Digital Design using Digilent FPGA Boards – by Richard E. Haskell & Darrin M. Hanna
This book uses over 75 examples to show you how to get started designing digital circuits in VHDL or Verilog, simulate them, and quickly and easily download them to your Basys™, Nexys2™, or Nexys3™ board. Get up and running quickly from the basics to the 7-segment display, memory, VGA port, PS/2 port, and more – step-by-step, by example!
A major revolution in digital design has taken place over the past decade. Field programmable gate arrays (FPGAs) can now contain over a million equivalent logic gates and tens of thousands of flip-flops. This means that it is not possible to use traditional methods of logic design involving the drawing of logic diagrams when the digital circuit may contain thousands of gates. The reality is that today digital systems are designed by writing software in the form of hardware description languages (HDLs). The most common HDLs used today are VHDL and Verilog. Both are in widespread use. When using these hardware description languages the designer typically describes thebehavior of the logic circuit rather than writing traditional Boolean logic equations. Computer-aided design tools are used to both simulate the VHDL or Verilog design and to synthesize the design to actual hardware.
This book assumes no previous knowledge of digital design. You start at the beginning learning about basic gates, logic equations, Boolean algebra, and Karnaugh maps. In over 75 examples we show you how to design digital circuits using VHDL or Verilog, simulate them using the Aldec Active-HDL simulator, and synthesize the designs to a Xilinx Spartan3E FPGA on either the Basys™, Nexys2™, or Nexys3™ FPGA board. A free student edition of Active-HDL simulator is available from Aldec Inc (www.aldec.com). To synthesize your design to a Spartan3E or Spartan 6 FPGA, you will need to download the Free ISE WebPACK from Xilinx Inc.(www.xilinx.com) The Xilinx synthesis tools are called from within the Aldec Active-HDL integrated GUI. We will use the Adept 2 utility to download your synthesized design to the Xilinx FPGA. The Adept 2.8.1 software suite can be download free from Digilent, Inc.
Table of Contents:
- 1. Introduction
- 2. Basic Logic Gates
- 3. Boolean Algebra and Logic Equations
- 4. Implementing Digital Circuits
- 5. Combinational Logic
- 6. Arithmetic Circuits
- 7. Sequential Logic
- 8. Finite State Machines
- 9. Datapaths and Control Units
- 10. Integrating the Datapath and Control Unit
- 11. Memory
- 12. VGA Controller
- 13. PS/2 Port
- Appendix A – Aldec Active-HDL Tutorial
- Appendix B – Number Systems
- Appendix C – Making a Turnkey System
- Appendix D – Digilent FPGA Boards Comparison Chart
- Appendix E – Installing the Xilinx ISE/WebPACK, Aldec Active-HDL, and Digilent Adept2 Software
- Appendix F – VHDL/Verilog Quick Reference Guide
Important Notes on Software and Hardware Versions
To program a Basys2 or Nexys2 board, you must use a “front end” design tool to create a source file that defines the intended circuit, and “back end” tools to synthesize the source file and download it to the board. Xilinx’s free Webpack software contains all needed tools, including source file editors, a synthesizer, and downloader. Aldec also produces a free front-end tool that can be used to create source files. Called Active-HDL, this front-end design tool presents a more student-friendly design interface, and it can automatically route design files to Xilinx’s back-end tools. The authors recommend Active-HDL due to its more intuitive interface.
If you are using a Basys board, you must use the user constraints file (.ucf) file for the Basys board (basys.ucf) available at http://www.lbebooks.com/downloads.htm
If you are using a Basys2 board, you must use the user constraints file (.ucf) file for the Basys2 board (basys2board.ucf) available at http://www.lbebooks.com/downloads.htm and you must download the Adept 2.1 (or above) software from theAdept Software page.
You cannot use Adept 1.10 with the Basys2 board.