Product Description
The Nexys 4 DDR is a drop-in replacement for our cellular RAM-based Nexys boards. Featuring the same Artix™-7 field programmable gate array (FPGA) from Xilinx®, the Nexys 4 DDR is a ready-to-use digital circuit development platform designed to bring additional industry applications into the classroom environment. The Artix-7 FPGA is optimized for high-performance logic, and offers more capacity, higher performance, and more resources than earlier designs. With its large, high-capacity FPGA (Xilinx part number XC7A100T-1CSG324C) and collection of USB, Ethernet, and other ports, the Nexys 4 DDR can host designs ranging from introductory combinational circuits to powerful embedded processors. Several built-in peripherals, including an accelerometer, a temperature sensor, MEMs digital microphone, speaker amplifier, and plenty of I/O devices allow the Nexys 4 DDR to be used for a wide range of designs without needing any other components. The most notable improvement is the replacement of the 16 MiB CellularRAM with a 128 MiB DDR2 SDRAM memory. Digilent will provide a VHDL reference module that wraps the complexity of a DDR2 controller and is backwards compatible with the asynchronous SRAM interface of the CellularRAM, with certain limitations.
The Nexys 4 DDR is compatible with Xilinx’s new high-performance Vivado® Design Suite as well as the ISE® toolset, which includes ChipScope™ and EDK. Xilinx offers free WebPACK™ versions of these tool sets, so designs can be implemented at no additional cost.
Support Materials
Datasheet (PDF)Schematics (PDF)
For all other material:
Stats:
Processor/IC: Xilinx Artix-7 FPGA XC7A100T-1CSG324C
Connector(s):
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UART/JTAG USB port
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Pmod port for XADC signals
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Audio connector
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Ethernet connector
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USB host connector
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microSD card connector
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12-bit VGA output
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Four Pmod ports
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Power jack
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Programming: Vivado Design Suite as well as the ISE toolset
Features:
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Xilinx Artix-7 FPGA XC7A100T-1CSG324C
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15,850 logic slices, each with four 6-input LUTs and 8 flip-flops
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4,860 Kbits of fast block RAM
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Six clock management tiles, each with phase-locked loop (PLL)
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240 DSP slices
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Internal clock speeds exceeding 450 MHz
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On-chip analog-to-digital converter (XADC)
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128 MiB DDR2
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Serial Flash
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Digilent USB-JTAG port for FPGA programming and communication
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microSD card connector
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Ships with rugged plastic case and USB cable
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USB-UART Bridge
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10/100 Ethernet PHY
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PWM audio output
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3-axis accelerometer
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16 user switches
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16 user LEDs
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Two tri-color LEDs
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PDM microphone
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Temperature sensor
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Two 4-digit 7-segment displays
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USB HID Host for mice, keyboards and memory sticks
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Pmod for XADC signals
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12-bit VGA output
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Four Pmod ports